ASP-DAC 2019: Asia and South Pacific Design Automation Conference
- Call for paper, ranking, acceptance rate,
submission deadline, notification date, conference location, submission guidelines, and other important details
This article provides the call for paper, ranking, acceptance rate,
submission deadline, notification date, conference location, submission guidelines, and other important details of ASP-DAC 2019: Asia and South Pacific Design Automation Conference all at one place.
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Conference Location
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Tokyo Odaiba Waterfront, Japan
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Conference Date
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2019-01-21
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Notification Date
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2018-09-10
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Submission Deadline
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2018-07-06
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Conference Website and Submission Link
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http://www.aspdac.com/aspdac2019/
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Conference Ranking
Asia and South Pacific Design Automation Conference ranking based on CCF, Core, and Qualis is shown below:
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CCF Ranking
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C
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Core Ranking
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Qualis Ranking
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A2
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Click here to check the ranking of any conference.
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About CCF Ranking: The Chinese Computing Federation (CCF) Ranking provides a ranking of peer-reviewed journals and conferences in the field of computer science.
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About Core Ranking: The CORE Conference Ranking is a measure to assess the major conference in the computing field. This ranking is governed by the CORE Executive Committee. To know more about Core ranking, visit Core ranking portal.
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About Qualis Ranking: This conference ranking is published by the Brazilian ministry of education. It uses the h-index as a performance metric to rank conferences. Conferences are classified into performance groups that range from A1 (to the best), A2, B1, B2,..., B5 (to the wost). To know more about qualis ranking, visit here
Conference Acceptance Rate
Below is the acceptance rate of Asia and South Pacific Design Automation Conference conference for the last few years:
| Year |
Submitted Papers |
Accepted Papers |
Accepted Percentage/Acceptance Rate |
We are working hard to collect and update the acceptance rate details of the conferences for recent years. However, you can consider the above (if available) acceptance rates to predict the average chances of acceptance of your research paper at this conference.
Conference Call for paper
Aims of the Conference:ASP-DAC 2019 is the 24th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.Areas of Interest:Original papers in, but not limited to, the following areas are invited.1. System-Level Modeling and Design Methodology:1.1. HW/SW co-design, co-simulation and co-verification1.2. System-level design exploration, synthesis and optimization1.3. Model- and component-based embedded system/software design1.4. System-level formal verification1.5. System-level modeling, simulation and validation tools/methodology2. Embedded System Architecture and Design:2.1. Many- and multi-core SoC architecture2.2. Reconfigurable and self-adaptive SoC architecture2.3. IP/platform-based SoC design2.4. Domain-specific architecture2.5. Dependable architecture2.6. Machine learning architecture2.7. Cyber physical system2.8. Storage system and memory architecture2.9. Internet of things3. Interconnect, Network, and Communication-Centric Design:3.1. Communication-centric system design, application, and simulation3.2. Networks-on-chip and NoC-based system design3.3. Inter/intra-chip interconnect and network, and interface and I/O3.4. Communication traffic and modeling3.5. Optical/photonic interconnect and network3.6. Rack-scale interconnect and network3.7. Emerging interconnect technology and application4. Embedded Software:4.1. Kernel, middleware and virtual machine4.2. Compiler and toolchain4.3. Real-time system4.4. Resource allocation for heterogeneous computing platform4.5. Storage software and application4.6. Human-computer interface4.7. System verification and analysis5. Device/Circuit-Level Modeling, Simulation and Verification:5.1. Device/circuit/interconnect modeling and analysis5.2. Device/circuit-level simulation tool and methodology5.3. RTL and gate-leveling modeling, simulation and verification5.4. Circuit-level formal verification6. Analog, RF and Mixed Signal:6.1. Analog/mixed-signal/RF synthesis6.2. Analog layout, verification and simulation techniques6.3. Noise analysis6.4. High-frequency electromagnetic simulation of circuit6.5. Mixed-signal design consideration6.6. Power-aware analog circuit/system design6.7. Analog/mixed-signal modeling and simulation techniques6.8. CAD for memory circuits7. Power Analysis, Low Power Design, and Thermal Management:7.1. Power modeling, analysis and simulation7.2. Low-power design and methodology7.3. Thermal aware design7.4. Architectural low-power design technique7.5. Energy harvesting and battery management8. Logic/High-Level Synthesis and Optimization:8.1. High-level synthesis tool and methodology8.2. Combinational, sequential and asynchronous logic synthesis8.3. Logic synthesis and physical design technique for FPGA8.4. Technology mapping9. Physical Design:9.1. Floorplanning, partitioning and placement9.2. Interconnect planning and synthesis9.3. Placement and routing optimization9.4. Clock network synthesis9.5. Post layout and post-silicon optimization9.6. Package/PCB/3D-IC routing10. Design for Manufacturability and Reliability:10.1. Reticle enhancement, lithography-related design and optimization10.2. Resilience under manufacturing variation10.3. Design for manufacturability, yield, and defect tolerance10.4. Reliability, aging and soft error analysis10.5. Design for reliability, aging, and robustness11. Timing and Signal/Power Integrity:11.1. Deterministic/statistical timing and performance analysis and optimization11.2. Power/ground and package modeling, analysis and optimization11.3. Signal/power integrity, EM modeling and analysis11.4. Extraction, TSV and package modeling11.5. 2D/3D on-chip power delivery network analysis and optimization12. Test and Design for Testability:12.1. ATPG, BIST and DFT12.2. Fault modeling and simulation12.3. System test and 3D IC test12.4. Online test and fault tolerance12.5. Memory test and repair12.6. Analog and mixed-signal/RF test13. Security and Fault-Tolerant System:13.1. Security modeling and analysis13.2. Architecture, tool and methodology for secure hardware13.3. Design for security and security primitive13.4. Cross-layer security13.5. Fault analysis, detect and tolerance14. Emerging Technology:14.1. New transistor/device and process technology: spintronic, phase-change, single-electron etc.14.2. CAD for nanotechnology, MEMS, 3D IC, quantum computing etc.14.3. Biochip and biodata processing etc.15. Emerging Application:15.1. Biomedical application15.2. Big data application15.3. Advanced multimedia application15.4. Energy-storage/smart-grid/smart-building design and optimization15.5. Artificial intelligence hardware and systems15.6. Automotive system design and optimization15.7. ElectromobilityPlease note that each paper shall be accompanied by at least one different conference registration at the speaker’s registration rate (e.g., two speaker registrations are needed for presenting two accepted papers). But any registered co-author can present the work at the conference. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by the author of the paper. ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, and journals.
Submission Deadline
ASP-DAC 2019: Asia and South Pacific Design Automation Conference submission deadline is 2018-07-06.
Note: It is generally recommended to submit your conference paper
on or before the submission deadline. Generally, conferences do not
encourage to submit the research paper after the deadline is over.
In rare scenarios, conferences extend their deadline. Decision about the
extension of the deadline is generally updated on the official conference webpage.
Notification date
Notification date of ASP-DAC 2019: Asia and South Pacific Design Automation Conference is 2018-09-10.
Note: This is the date on which conference announces the result about acceptance or rejection of submitted papers. If your research paper is accepted, the conference will request you to submit the camera ready version of your research paper by the due date. Due date to submit the camera ready version of the paper is generally posted on the official web page of the conferences or notified to you via. email.
Conference Date
ASP-DAC 2019: Asia and South Pacific Design Automation Conference will start on 2019-01-21.
Note: This is the date on which the conference starts.
Conference Location
ASP-DAC 2019: Asia and South Pacific Design Automation Conference will be organized at Tokyo Odaiba Waterfront, Japan. This is the place where the conference is organized and the research paper is to be presented.
