RISCV-HPCAsia 2024 : Third International workshop on RISC-V for HPC
RISCV-HPCAsia 2024 : Third International workshop on RISC-V for HPC

RISCV-HPCAsia 2024 : Third International workshop on RISC-V for HPC

Nagoya, Japan
Event Date: January 25, 2024 - January 25, 2024
Submission Deadline: November 28, 2023
Notification of Acceptance: November 12, 2023
Camera Ready Version Due: December 20, 2023

Call for Papers

Call for Papers

Third International workshop on RISC-V for HPC (RISC-V HPC)

Held in conjunction with HPC Asia on 25th January 2024

Submission deadline extended to: 28th November 2023 (AoE)
Author Notification: 12th December 2023
Camera ready papers: 20th December 2023

This workshop will be held in conjunction with HPC Asia 2024 in Nagoya, Japan between 8:30 a.m. and noon on January 25th 2024.

RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and in 2022 the ten billionth RISC-V core was shipped, to date it has yet to gain traction in HPC.

The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. There are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before. An example of this is vectorisation extension which provides important performance advantages for HPC workloads but was only standardised in early 2022, and-so we are only now seeing mature CPUs that fully implement this.

The open and standardised nature of RISC-V means that the large, and growing community, can be involved in shaping the standard and tooling. This is important from two perspectives, firstly it is our opportunity in the HPC community to help shape the future of RISC-V to ensure that it is suitable for the next generation of supercomputers. Secondly, whilst there are a wide variety of RISC-V CPUs currently available, the standard nature of the tooling means that very often the same software ecosystem comprising the compiler, operating system, and libraries will run across these whilst requiring few changes.

This workshop aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. By sharing benefits of the architecture, success stories, and techniques we hope to further popularise the technology and increase involvement by the community.

Call for papers and workshop topics

We invite submissions of high-quality, original research results and works-in-progress on RISC-V with a general connection to HPC. Topics of interest for this workshop include (but are not limited to):

* Example use-cases and case-studies that use RISC-V
* Lessons learnt from leveraging RISC-V in HPC
* Industry papers exploring the use of RISC-V
* The porting of codes to RISC-V
* Novel hardware and accelerators built upon RISC-V
* Tools and techniques to aid in the use of RISC-V for HPC
* Developments in HPC libraries to port them to RISC-V
* Enhancements to RISC-V to make the architecture more suited for HPC
* Compiler and runtime support for RISC-V
* The RISC-V ecosystem
* Future gazing how RISC-V might evolve the HPC community
* And anything else related to RISC-V and HPC!

Paper submission details

Authors are invited to submit unpublished, original work, and accepted papers will appear in the workshop proceedings. Following the main HPCAsia paper guidelines, where manuscripts should be submitted for review in a single-column format and be at most 18 pages including figures and references, formatted according to the ACM Proceedings Style.

See for further details and submission instructions

Organising committee

* Michael Wong (Codeplay)
* Nick Brown (EPCC at the University of Edinburgh)
* John Davis


RISCV-HPCAsia 2024 : Third International workshop on RISC-V for HPC will take place in Nagoya, Japan. It’s a 1 day event starting on Jan 25, 2024 (Thursday) and will be winded up on Jan 25, 2024 (Thursday).

RISCV-HPCAsia 2024 falls under the following areas: RISC-V, HPC, SUPERCOMPUTING, NOVEL ARCHITECTURES, etc. Submissions for this Workshop can be made by Nov 28, 2023. Authors can expect the result of submission by Nov 12, 2023. Upon acceptance, authors should submit the final version of the manuscript on or before Dec 20, 2023 to the official website of the Workshop.

Please check the official event website for possible changes before you make any travelling arrangements. Generally, events are strict with their deadlines. It is advisable to check the official website for all the deadlines.

Other Details of the RISCV-HPCAsia 2024

  • Short Name: RISCV-HPCAsia 2024
  • Full Name: Third International workshop on RISC-V for HPC
  • Timing: 09:00 AM-06:00 PM (expected)
  • Fees: Check the official website of RISCV-HPCAsia 2024
  • Event Type: Workshop
  • Website Link:
  • Location/Address: Nagoya, Japan

Credits and Sources

[1] RISCV-HPCAsia 2024 : Third International workshop on RISC-V for HPC

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