SOCC 2022 : 35th IEEE International System-on-Chip Conference (Extended)

=== EXTENDED CALL FOR PAPERS ===

=====================================================
= 35th IEEE International System-on-Chip Conference =
= Titanic Belfast, Northern Ireland =
= September 5-8, 2022 =
= www.ieee-socc.org =
=====================================================

Deadlines
=========
Regular and Design Track Papers: May 16, 2022
Proposals for Special Sessions: May 16, 2022
Notification of acceptance: June 27, 2022
Final camera‐ready paper due: July 18, 2022

“The impact of AI/ML computing on System-on-Chip and Semiconductor Technologies”

System-on-Chip (SoC) devices, comprising digital, analog, optical, RF, and Micro-Electro-Mechanical
Systems (MEMS), are the foundation of ubiquitous computing and the communication, entertainment,
medical and logistics technologies underpinning emerging “Digital Societies”.

Recent advances in systems, packaging and process technologies are enabling the computation of
hundreds of teraflops per chip and  unleashing the massive rise of Artificial Intelligence-enabled products
and applications.  This incredible demand for integration and computing per square millimetre of silicon
creates new challenges with respect to storage, memory, security, reliability, power, on-chip communication,
packaging and the management of design and verification.

For 35 years the IEEE International System-on-Chip Conference (SOCC) has been the premier forum for
sharing the latest advancements in SoC architecture, systems, logic and circuit design, process technology,
test, design tools, and applications. We proudly continue this tradition with the 2022 conference at the
birthplace of the Titanic in Belfast, Northern Ireland. 

Areas of Interest
=================
Papers are invited which address new and previously unpublished results in all areas related to SoC,
including but not limited to:

o Devices and Platforms for accelerated AI/ML computing 
 SoCs for AI — Evolvable, adaptable, and reconfigurable architectures — Architectures for
intelligent hardware systems — On-chip learning and adaption — Neuromorphic chips — Low-power and
low-area SoCs for smart IoT — Sensing, Imaging and Vision — In-memory computation — In-sensor processing

o Emerging and Disruptive Technologies:
 Many-core architectures — Data processing units (DPUs) — General purpose GPU (GPGPU) computing — Embedded accelerators — Server on a Chip — Cortical processors — Neuronal and neuromorphic computing — Beyond CMOS solutions —Quantum computing —
Cloud infrastructure solutions — Futuristic development and optimization tools.

o Design for Secure and Reliable Systems:
 Hardware-assisted security — Embedded security architectures — Trusted computing architectures — Cyber resilient architectures —
Embedded encryption — Quantum-safe cryptography — Homomorphic encryption — SoC solutions for real-time, high reliability
and safety applications — Self-healing SoCs — Soft-error and variation-tolerant design

o Heterogeneous and Many-Core SoC Architectures:
 On-chip interconnect — Network on Chip (NoC) and multicore architectures — Memory architecture for multicore computing —
Heterogeneous computing — High-performance mobile SoCs — Parallel programming and software models — Multi-die packaging —
Integration — Chiplets/Dielets

o Circuits and Systems:
 RF, analog, mixed-signal — Biomedical — Wireline & Wireless Communication — 5G Circuits and Devices —
Reconfigurable and programmable circuits — MEMS and Sensors — Photonics

o Low Power Design:
 “Green” circuits & systems — Low power methodologies — Power/energy/ thermal aware architecture design —
Multi-domain power/energy management — Energy harvesting

o Design Methodologies and Development Flows:
 Heterogeneous design flows — Agile and Feature-Driven HW Development — HW-SW co-design, reconfiguration and debug —
System level design methodology and tools — Design validation and verification — Design for Testability,
test synthesis, embedded test

Submission of Papers and Special Session Proposals
==================================================
o Regular Papers: 
 limited to six double-column IEEE formatted pages.
 All submissions will receive a double-blind peer review. Accepted papers presented at the conference will be included
in the SOCC proceedings and will be submitted for inclusion into IEEE Xplore® subject to meeting IEEE Xplore’s scope
and quality requirements.

o Special Session Proposals:
 Must include title, topic rationale, organizer’s short bio, and a list of contributed papers.
Submit directly to [email protected].

For detailed formatting instructions, submission & publication guidelines, refer to www.ieee-socc.org