DLonSC 2020 : 4th International Workshop on Deep Learning on Supercomputers

Topics include but are not limited to:

• DL as a novel approach of scientific computing

  • Emerging scientific applications driven by DL methods
  • Novel interactions between DL and traditional numerical simulation
  • Effectiveness and limitations of DL methods in scientific research
  • Algorithms and procedures to enhance reproducibility of scientific DL applications

• DL for science workflows

  • Data management through the life cycle of scientific DL applications
  • General algorithms and procedures for efficient and scalable DL training

• Scalable DL methods to address the challenges of demanding scientific applications

  • General algorithms and systems for large scale model serving for scientific use cases
  • New software, and enhancements to existing software, for scalable DL
  • DL communication optimization at scale
  • I/O optimization for DL at scale
  • DL performance evaluation and analysis on deployed systems
  • DL performance modeling and tuning of DL on supercomputers
  • DL benchmarks on supercomputers

• Novel hardware designs for more efficient DL

  • Processors, accelerators, memory hierarchy, interconnect changes with impact on deep learning in the HPC context

As part of the reproducibility initiative, the workshop requires authors to provide information such as the algorithms, software releases, datasets, and hardware configurations used. For performance evaluation studies, we will encourage authors to use well-known benchmarks or applications with open accessible datasets: for example, MLPerf and ResNet-50 with the ImageNet-1K dataset.

Important Dates

• Technical paper due: Mar 31st, 2020
• Acceptance notification: Apr 16th, 2020
• Camera ready: May 15th, 2020
• Workshop date: June 25th, 2020

Paper Submission

Authors are invited to submit unpublished, original work with a minimum of 6 pages and a maximum of 12 pages in single column text with LNCS style. All submissions should be in LNCS format and submitted using linklings tentatively.

Organizing Committee

• Valeriu Codreanu (co-chair), SURFsara, Netherlands
• Ian Foster (co-chair), UChicago & ANL, USA
• Zhao Zhang (co-chair), TACC, USA
• Weijia Xu (proceeding chair), TACC, USA
• Ahmed Al-Jarro, Fujitsu Laboratories of Europe, UK
• Takuya Akiba, Preferred Networks, Japan
• Thomas S. Brettin, ANL, USA
• Maxwell Cai, SURFsara, Netherlands
• Erich Elsen, DeepMind, USA
• Steve Farrell, LBNL, USA
• Song Feng, IBM Research, USA
• Boris Ginsburg, Nvidia, USA
• Torsten Hoefler, ETH, Switzerland
• Jessy Li, UT Austin, USA
• Zhengchun Liu, ANL, USA
• Peter Messmer, Nvidia, USA
• Damian Podareanu, SURFsara, Netherlands
• Simon Portegies Zwart, Leiden Observatory, Netherlands
• Qifan Pu, Google, USA
• Arvind Ramanathan, ANL, USA
• Vikram Saletore, Intel, USA
• Mikhail E. Smorkalov, Huawei, Russia
• Rob Schreiber, Cerebras, USA
• Dan Stanzione, TACC, USA
• Rick Stevens, UChicago & ANL, USA
• Wei Tan, Citadel, USA
• Jordi Torres, Barcelona Supercomputing Center, Spain
• Daniela Ushizima, LBNL, USA
• Sofia Vallecorsa , CERN, Switzerland
• David Walling, TACC, USA
• Markus Weimer, Microsoft, USA
• Kathy Yelick, UC Berkeley & LBNL, USA
• Huazhe Zhang, Facebook, USA