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HARDWARE ARCHITECTURE
HPC
HETEROGENEOUS COMPUTING
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About |
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The development of ever larger and more energy-efficient computer systems in recent years has led to more and more systems with heterogeneous computing units (CPUs, GPUs or FPGAS) and systems with heterogeneous storage systems (High Memory Bandwidth). With the rise of persistent memory, attached to the PCIe bus or to the memory DIMMs, the border between storage and memory becomes more and more fluid. Other systems offer different types of compute nodes, so that a group of nodes build the accelerator (modular supercomputing). Hierarchical storage architectures, for example using burst buffers, try to overcome the IO problems. Programming such a system can be a real challenge along with locality, scheduling, load balancing, concurrency and so on. This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries and runtime systems that improve the performance and productivity of applications on these systems. The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems. |
Call for Papers |
Workshop Scope and GoalsThe current computing landscape has gone through an ever-increasing rate of change and innovation. This change has been driven by the relentless need to improve the energy-efficient, memory, and compute throughput at all levels of the architectural hierarchy. Although the amount of data that has to be organized by today's systems posed new challenges to the architecture, which can no longer be solved with classical, homogeneous design. Improvements in all of those areas have led Heterogeneous systems to become the norm rather than the exception. Heterogeneous computing leverages a diverse set of computing (CPU, GPU, FPGA, TPU ...) and Memory (HBM, Persistent Memory, Coherent PCI protocols, etc ..), hierarchical storage systems and units to accelerate the execution of a diverse set of applications. Emerging and existing areas such as DeepLearing, BigData, Cloud Computing, Edge-Computing, Real-time systems, High-Performance Computing and others have seen a real benefit due to Heterogenous computer architectures. These new heterogeneous architectures often also require the development of new applications and programming models, in order to satisfy these new architectures and to fully utilize these capacities. This workshop focuses on understanding the implications of heterogeneous designs at all levels of the computing system stack, such as hardware, compiler optimizations, porting of applications, and developing programming environments for current and emerging systems in all the above-mentioned areas. It seeks to ground heterogeneous system design research through studies of application kernels and/or whole applications, as well as shed light on new tools, libraries and runtime systems that improve the performance and productivity of applications on heterogeneous systems. The goal of this workshop is to bring together researchers and practitioners who are at the forefront of Heterogeneous computing in order to learn the opportunities and challenges in future Heterogeneous system design trends and thus help influence the next trends in this area. Topics of interest for workshop submissions include (but are not limited to):
ProceedingsThe proceedings of this workshops will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library. Submission InstructionsPapers should present original research and should provide sufficient background material to make them accessible to the broader community. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for for latex or word for details. Submissions will be judged based on relevance, significance, originality, correctness and clarity. Submission site: https://easychair.org/conferences/?conf=ashes2020 Journal Special IssueThe best papers of AsHES 2020 will be invited to a Special Issue on Topics on Heterogeneous Computing of the Elsevier International Journal on Parallel Computing (PARCO) (speical issues list). Important Dates (AoE)Paper Submission: Paper Notification: March 2, 2020 Camera-Ready Papers Due: March 17, 2020 |
Summary |
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AsHES 2020 : The Tenth International Workshop on Accelerators and Hybrid Exascale Systems will take place in New Orleans, USA. It’s a 1 day event starting on May 17, 2020 (Sunday) and will be winded up on May 17, 2020 (Sunday). AsHES 2020 falls under the following areas: HARDWARE ARCHITECTURE, HPC, HETEROGENEOUS COMPUTING, etc. Submissions for this Workshop can be made by Feb 07, 2020. Authors can expect the result of submission by Mar 02, 2020. Upon acceptance, authors should submit the final version of the manuscript on or before Mar 17, 2020 to the official website of the Workshop. Please check the official event website for possible changes before you make any travelling arrangements. Generally, events are strict with their deadlines. It is advisable to check the official website for all the deadlines. Other Details of the AsHES 2020
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Credits and Sources |
| [1] AsHES 2020 : The Tenth International Workshop on Accelerators and Hybrid Exascale Systems |
